Carry propagate adder circuits are typically coupled in parallel for receiving input bits in parallel and for providing output sum bits in parallel. A carry input bit is coupled to a single ended carry line which is coupled to each adder circuit. The input carry bit in conjunction with the output sum bit of each adder circuit cause a carry bit having either a high or a low logic level to propagate along the carry line. Conventional precharging circuitry is used to precharge the carry line to a predetermined logic level before the sum operation is executed. An output carry bit is provided by the carry line. However, the correct sum is not provided until the carry bit has propagated along the carry line at each adder circuit. The disadvantage of using a plurality of parallel connected carry propagate adder circuits is that the addition process is very slow due to the time required for the carry bit to be propagated along each adder circuit.